1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, it relates to a semiconductor memory device and a method for making the same in which soft errors induced by a particles or the like are hard to occur.
2. Description of the Prior Art
A semiconductor memory device comprising one-transistor type dynamic memory cell is widely used for a memory capacity of 4 Kbit to 1 Mbit, since its structure is simple and suitable for high integration. The one-transistor type dynamic memory cell, comprising a charge storage capacitor and a write/read transistor, has a problem of soft errors, that is, carriers generated in the silicon substrate by an ionizing radiation such as a particles and the like are collected in the memory cell and the stored contents are destroyed.
Various memory cells are proposed which are devised to have protective structures against such soft errors. FIG. 1 is a cross sectional view of a memory cell having a Hi-C structure disclosed in, for example, IEEE. Tans. Electron Devices, vol. ED-25 (1978), pp. 33-41, "The Hi-C RAM Cell Concept", by A. F. Tasch et al.. The memory cell of FIG. 1 comprises a P.sup.- type silicon substrate 1, a field oxide film 2 for isolation, a channel stop P.sup.+ region 3 for isolation, an insulator film 4 for a capacitor, a cell plate electrode 5 forming an opposed electrode of a charge storage capacitor, a word line 6 associated with a write/read transistor, an N.sup.+ region 7 connected to a bit line, a contact hole 8, a bit line 9, and an N.sup.+ region 11 and a P region 12 related to the Hi-C structure.
In this memory cell, a P-N junction comprised of the N.sup.+ region 11 and the P region 12 is formed in the silicon substrate under the charge storage capacitor and then the charge storage capacitance is increased by this P-N junction capacitance added in parallel to the MOS capacitance. In this case, the impurity concentration in the P region 12 is fairly high compared with that in the silicon substrate 1. This structure restrains the extension of the depletion layer, so that the funneling phenomenon is suppressed. This structure also serves as a barrier against carriers diffusing from the substrate 1 into the N.sup.+ region 4, remarkably reducing the number of carriers to be collected, thereby reducing occurrences of soft errors.
However, in the conventional semiconductor memory device, there was no measure to cope with the collection of carriers in the N.sup.+ region 7 connected to the bit line 9. Namely, the conventional device is not protected against soft errors in this portion.
Meanwhile, a buried N type grid in a P type substrate for protection against radiation induced charge collection is described in IEDM Tech. Dig., 1981, pp. 40-43, by M. R. Wordeman et al. and a buried P.sup.+ type layer in a P type substrate is described in Japanese Patent Laying-Open Gazette 107667/1983 (corresponding to the U.S. Pat. application Ser. No. 333,230). However, there still exists some room to make further improvement in relation to soft errors in a prior art semiconductor memory device.